The ability to effectively and efficiently test and/or validate designs is becoming increasingly important. Typical data processing system designs are rapidly increasing in complexity and furthermore are including circuit blocks designed by a variety of different sources or companies. So called system-on-chip (SoC) designs that integrate a large number of functional elements on a single integrated circuit have strong advantages in terms of cost and performance, but require significant amounts of validation and testing before the designs can be reliably released for manufacture. This validation and testing requirement is becoming a bottleneck in getting new systems into the market place. Consequently, measures that can improve the efficiency and effectiveness of such validation and testing of designs are strongly advantageous.
One known approach that can be used to seek to validate a SoC design is to construct a system under verification representing the design of the data processing system to be tested, where the system under verification includes a number of models modelling particular parts of the system design. The system under verification may include a component model representing one or more hardware components of the data processing system, and this component model may be coupled via an interface module with other portions of the system under verification.
Sequences of verification tests can then be performed upon the system under verification to cause various transactions to take place between different portions of the system in order to test correct operation, each transaction defining one or more transfers between specified portions of the system. However, it can be difficult to efficiently verify corner cases (i.e. problems or situations that occur only outside of normal operating parameters) in a system design purely by performing sequences of transactions within the system under verification. Accordingly, it is known to seek to verify corner cases by substituting one or more component models with transactors, a transactor being a simplified model which can be viewed externally as modelling the same hardware component(s) as the component model which it is substituted for, but which internally is significantly simplified, and designed specifically to perform one or more test actions which can be provided to seek to test and verify corner cases in the system design.
One example of such a transactor is an eXtensible Verification Component (XVC) which can be arranged to execute certain test scenarios. Often a number of XVCs may be substituted into the design, with the actions of the separate XVCs being coordinated by a test manager. The test actions performed by the XVCs can take a variety of forms, and hence for example considering an XVC used to represent a master device, that XVC may perform test actions to either drive directed FRBM (File Reader BUS Master) format vectors onto an associated bus, or to generate random patterns of transfers constrained by a user configuration file. FRBM is an ARM Limited proprietary format used to stimulate AMBA bus signals, for example AHB, APB or AXI, in order to perform read and write transfers on a bus interconnect.
Transactors such as the above XVC components can often provide a more direct route to exercising design corner cases than would be the case if instead a particular component model is used, and this can enable verification closure to be completed more efficiently. However, one disadvantage of such an approach is that system integrity is potentially compromised at each stage of the verification process due to the absence of the actual component models that have been substituted. In particular, due to the substitution of a component model with such a transactor, the revised system under verification then less precisely models the actual design of the data processing system seeking to be verified. Another disadvantage is that it is often very time consuming for a verification engineer to produce a set of test vectors to be executed by the transactor to place the system into a given state ready for testing.
The article “Integrating Verification Components” by Leonardo de Moura et al, Computer Science Laboratory, SRI International, appearing on the Internet at http://vstte.ethz.ch/Files/demoura-owre-ruess-rushby-shankar.pdf, discusses the merits of directly connected or embedded verification components. Verification components replace system components for DUT (Device under Test) testing, and are analogous to the ARM XVC methodology discussed earlier.
The article “Spying on Components: A Runtime Verification Technique”, by Mike Barneff et al, Microsoft Research, appearing on the Internet at http://research.microsoft.com/users/schulte/Papers/SpyingOnComponents(savcbs2001) .pdf, discusses the use of runtime monitors to check the specification of a component.
The CADI interface developed by ARM Limited, Cambridge, United Kingdom, in connection with its RealView SoC Designer product provides an interface to a model that allows a debugger to access the internal state of the model and perform memory access to the rest of the system. These memory accesses should not change the internal state of the system e.g. cache state, cycle count, or bus state. However a write access to memory or an internal register will change the state of that memory location or register.
In the field of testing designs at an RTL (Register Transfer Language) level, ARM Limited developed a RealView modelling environment which included a test interface controller (TIC). The TIC can be used as a bus master in a system in order to inject test vectors, and hence is essentially a verification component that connects to the system bus and is controlled via an external control mechanism outside of the system under test. Further discussion of the TIC module can be found in commonly assigned U.S. Pat. No. 6,463,488.
It would be desirable to provide an improved technique for verifying a design of a data processing system which enables effective testing of corner cases whilst alleviating impact on system integrity whilst performing such testing.